International Journal of Advanced Information and Communication Technology


Multiplier Design using Adaptive Hold Logic

S. Prema, S. Divya, G. Divya Karunya, R. Kokila, KPR Institute of Engineering and Technology, Coimbatore, Tamilnadu, India.

DOI : 01.0401/ijaict.2016.11.05

International Journal of Advanced Information and Communication Technology

Received On : April 13, 2019

Revised On : May 18, 2019

Accepted On : June 12, 2019

Published On : July 05, 2019

Volume 06, Issue 07

Pages : 1093-1097

Abstract


Low power consumption and reduced time delay has been an important part in VLSI system design. Digital multipliers are key components of many high performance systems such as FIR filters, microprocessors and digital signal processors. The overall performance of these systems depends on the performance of the multipliers and if the multipliers are too slow, the performance of entire circuits will be reduced. Hence, it is important to design high performance multipliers. Therefore, a multiplier design with a novel Adaptive Hold Logic (AHL) is proposed. The multiplier is able to provide higher performance through the variable-latency and can adjust the AHL circuit to reduce maximum power consumption and delay. The timing violations are reduced based on the idea of razor flip flop and Adaptive Hold Logic. In the fixed-latency technique, usage of clock cycles is increased. The re-execution of clock cycles is reduced by using variable-latency. The experimental results show that our proposed architecture with column- and row-bypassing multipliers achieves better performance in power consumption and delay compared with fixed-latency column- and row-bypassing multipliers.

Keywords


Center tap, DC active filter, Grid connection system, Ripple current reduction, Single-phase isolated converter.

Cite this article


S. Prema, S. Divya, G. Divya Karunya, R. Kokila, “Multiplier Design using Adaptive Hold Logic” INTERNATIONAL JOURNAL OF ADVANCED INFORMATION AND COMMUNICATION TECHNOLOGY, pp.1093-1097, July 05, 2019.

Copyright


© 2019 S. Prema, S. Divya, G. Divya Karunya, R. Kokila. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.