Meenal R. Dadhe, Sanjay Tembhurne, GHRAET, RTMN University, Nagpur, India.
DOI : 01.0401/ijaict.2014.07.26
International Journal of Advanced Information and Communication Technology
Received On : December 10, 2017
Revised On : January 15, 2017
Accepted On : February 13, 2017
Published On : March 05, 2017
Volume 04, Issue 03
Pages : 635-637
Abstract
The main purpose of high-speed architecture of linear feedback shift register (LFSR) based on PN Sequence generator technique. It is used for various cryptography application and for designing encoder, decoder in different communication channel. Depend on the feedback polynomial total number of random sequence generator on LFSR. It is simple counter so its count maximum of 2n-1by using maximum feedback polynomial. Here in this work we implement LFSR by using VHDL to study the performance and analysis the behaviour of randomness .The analysis is conceded out to find number of gates, memory and speed requirement as the number of bits is increased. We proposed LFSR architecture based on serial, parallel, combined parallel and pipelining algorithm to minimize delay of the system.
Keywords
Linear Feedback Shift Register, VHDL.
Cite this article
Meenal R. Dadhe, Sanjay Tembhurne, “Design of High-Speed VLSI Architecture for LFSR with Maximum Length Feedback Polynomial ” INTERNATIONAL JOURNAL OF ADVANCED INFORMATION AND COMMUNICATION TECHNOLOGY, pp.635-637, March 05, 2017.
Copyright
© 2017 Meenal R. Dadhe, Sanjay Tembhurne. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.