Ms. Nikita N. Buradkar, Prof. Sanjay Tembhurne, GHRAET, RTMN University, Nagpur, India.
DOI : 01.0401/ijaict.2014.07.24
International Journal of Advanced Information and Communication Technology
Received On : December 15, 2017
Revised On : January 19, 2017
Accepted On : February 15, 2017
Published On : March 05, 2017
Volume 04, Issue 03
Pages : 628-630
Abstract
Low power consumption, high speed and smaller area are some of the most important aspects for the designing of any VLSI system. Area and speed are usually incompatible constraints so good design has to set the equilibrium between area and speed. Through work in this paper we try to determine the best solution to this problem. Vedic algorithm is most popularly used ancient algorithm which yields quicker results by using basic addition and multiplication technique. Vedic mathematics consists of 16 sutras. It covers explanation of several modern arithmetical terms. In this project various Vedic sutras are used for all type of reversible division process. To design circuit VHDL coding will be used (Very High Speed Integrated Circuits Hardware Description Language) by combining Boolean logic with ancient Vedic mathematical technique for obtaining high speed divisor for improving speed.
Keywords
Vedic Mathematics, Nikhilam Navatascaramam Dashatah, Vhdl Code.
Cite this article
Ms. Nikita N. Buradkar, Prof. Sanjay Tembhurne, “Design and Simulation of Vedic Divider using Reversible Logic” INTERNATIONAL JOURNAL OF ADVANCED INFORMATION AND COMMUNICATION TECHNOLOGY, pp.628-630, March 05, 2017.
Copyright
© 2017 Ms. Nikita N. Buradkar, Prof. Sanjay Tembhurne. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.