International Journal of Advanced Information and Communication Technology


A Low-Cost, Systematic Methodology for Soft Error Robustness of Logic Circuits

S. N. Sivasankari, Maria College of Engineering and Technology, Attoor, Tamilnadu, India.

D. Anuja, RVS College of Engineering, Coimbatore, Tamilnadu, India.

DOI : 01.0401/ijaict.2015.10.02

International Journal of Advanced Information and Communication Technology

Received On : September 08, 2017

Revised On : October 10, 2017

Accepted On : November 13, 2017

Published On : December 05, 2017

Volume 04, Issue 12

Pages : 777-780

Abstract


Due to current technology scaling trends such as shrinking feature sizes and decreasing supply voltages, circuit reliability is becoming more susceptible to radiation-induced transient faults (soft errors). Soft errors, which have been a great concern in memories, are now a main factor in reliability degradation of logic circuits as well. In this paper, present a systematic and integrated methodology for circuit robustness to soft errors. The proposed soft error rate (SER) reduction framework was based on redundancy addition and removal (RAR), which aims to eliminating those gates with large contribution to the overall SER. Several metrics and constraints are introduced to guide the RAR-based approach towards SER reduction. In this paper also integrate a resizing strategy as post-RAR additive SER optimization. The strategy can identify most critical gates to be upsized and thereby, minimize area and power overheads while maintaining a high level of soft error robustness. Experimental results show that the proposed RAR-based framework can achieve up to 70% reduction in output failure probability. On average, about 23% SER reduction is obtained with less than 4% area overhead.

Keywords


Gate Resizing, Redundancy Addition and Removal, Reliability, Soft Error Robustness, Soft Errors, Ser Rate. Single-Event Upset.

Cite this article


S. N. Sivasankari, D. Anuja, “A Low-Cost, Systematic Methodology for Soft Error Robustness of Logic Circuits” INTERNATIONAL JOURNAL OF ADVANCED INFORMATION AND COMMUNICATION TECHNOLOGY, pp.777-780, December 05, 2017.

Copyright


© 2017 S. N. Sivasankari, D. Anuja. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.