Sumit C. Katkar, Pragati Kene, Shubhangini Ugale, G. H. Raisoni Academy of Engineering and Technology, Nagpur, Maharashtra, India.
DOI : 01.0401/ijaict.2015.09.07
International Journal of Advanced Information and Communication Technology
Received On : August 10, 2017
Revised On : September 13, 2017
Accepted On : October 12, 2017
Published On : November 05, 2017
Volume 04, Issue 11
Pages : 762-766
Abstract
Multiplier Accumulator Unit (MAC) is a part of Digital Signal Processors. The speed of MAC depends on the speed of multiplier. The proposed MAC unit reduces the area by reducing the number of multiplication and addition in the multiplier unit. Increase in the speed of operation is achieved by the hierarchical nature of the Vedic multiplier unit. So by using an efficient Vedic multiplier which excels in terms of speed, power and area, the performance of MAC can be increased. For this fast method of multiplication based on ancient Indian Vedic mathematics is used. Among various method of multiplication in Vedic mathematics, Urdhva Tiryagbhyam is used and the multiplication is for 64 X 64 bits. Urdhva Tiryagbhyam is a general multiplication formula applicable to all cases of multiplication. It enables parallel generation of intermediate products, eliminates unwanted multiplication steps with zeros.
Keywords
MAC, Vedic Multiplier, VHDL, Ripple Carry (RC) Adder.
Cite this article
Sumit C. Katkar, Pragati Kene, Shubhangini Ugale, “Design of Efficient 64 Bit Mac Unit using Vedic Multiplier for DSP Application – A Review” INTERNATIONAL JOURNAL OF ADVANCED INFORMATION AND COMMUNICATION TECHNOLOGY, pp.762-766, November 05, 2017.
Copyright
© 2017 Sumit C. Katkar, Pragati Kene, Shubhangini Ugale. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.