Priyanka M. Zade, Prachi Pendke, Shubhangini Ugale, G.H. Raisoni Academy of Engineering and Technology, Nagpur, Maharashtra, India
A. B. Bavaskar, Priyadarshini College of Engineering, Nagpur, India.
DOI : 01.0401/ijaict.2014.07.19
International Journal of Advanced Information and Communication Technology
Received On : October 10, 2017
Revised On : November 21, 2017
Accepted On : December 12, 2017
Published On : January 05, 2017
Volume 04, Issue 01
Pages : 610-612
Abstract
PCI Express implements dual simplex link to transmit and receive data simultaneously on transmitter and receiver device.PCI Express employs packet to accomplish data transfer between devices. This paper presents the physical layer architecture of PCI Express 1.0a which ensures reliable transport of transaction layer packets (TLPs) and data link layer packets(DLLPs) on both transmitter and receiver side. The physical layer helps in reliable conveying with start and end bit to each data coming from transaction layer and data link layer on transmitter side and the packet is decoded on receiver side. For simulation of each sub block of both transmitter and receiver we are using Xilinx ISE software & for coding we employed Very High Speed Integrated Circuit Hardware Description Language (VHDL).
Keywords
PCI Express, Physical layer, VHDL.
Cite this article
Priyanka M. Zade, Prachi Pendke, Shubhangini Ugale, A. B. Bavaskar, “Design of the Physical Layer of PCI Express- A Review” INTERNATIONAL JOURNAL OF ADVANCED INFORMATION AND COMMUNICATION TECHNOLOGY, pp.610-612, January 05, 2017.
Copyright
© 2017 Priyanka M. Zade, Prachi Pendke, Shubhangini Ugale, A. B. Bavaskar. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.