M. Prakash, S. Karthick, C. Suba, S. Kishor, Bannari Amman Institute of Technology, Sathyamangalam, Tamilnadu, India.
DOI : 01.0401/ijaict.2014.07.03
International Journal of Advanced Information and Communication Technology
Received On : June 13, 2016
Revised On : July 20, 2016
Accepted On : August 12, 2016
Published On : September 05, 2016
Volume 03, Issue 09
Pages : 552-556
Abstract
A high speed processor depends greatly on the multiplier as it is one of the key hardware blocks in most digital signal processing system as well as in general processors. The various types of multipliers like Braun, Booth, Vedic, and Wallace Tree Multipliers are simulated using Hardware Description Language (HDL). The Simulated tool is Xilinx ISE 14.3. The major comparative analyses of these multipliers concentrate in number of LUT’s and LUT-FF Pairs. This paper mainly reduces the area level of the Processors. And also checks with these Multipliers are done on FPGA Spartan 6 and Vertex 5 kits.
Keywords
Braun, Booth, Vedic, Wallace Tree Multipliers, HDL Languages.
Cite this article
M. Prakash, S. Karthick, C. Suba, S. Kishor, “Simulation and Comparative Analysis of Different Types of Multipliers” INTERNATIONAL JOURNAL OF ADVANCED INFORMATION AND COMMUNICATION TECHNOLOGY, pp.552-556, September 05, 2016.
Copyright
© 2016 M. Prakash, S. Karthick, C. Suba, S. Kishor. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.