S. Karthiga Swathini, P. N. Palanisamy, Mahendra College of Engineering, Salem, Tamilnadu, India.
DOI : 01.0401/ijaict.2014.06.09
International Journal of Advanced Information and Communication Technology
Received On : April 10, 2016
Revised On : May 20, 2016
Accepted On : June 15, 2016
Published On : July 05, 2016
Volume 03, Issue 07
Pages : 512-516
Abstract
Current Mode Signaling Scheme-Bias is one of the efficient schemes to achieve high-speed and low power communica-tion over long On-Chip interconnects. In early days the repeaters and boosters circuits [4] are used to drive the on-chip interconnects. In this paper CMS scheme with various types of delay elements which is inserted in the circuit is used to analyze the performance in terms of power and tolerant variation.CMS scheme has an impor-tance that it has a trade-off between speed and power as in[1]. In addition, the voltage swing on the line is reduced in our proposed scheme as in [2]. By the inserting a conventional buffer as delay element the improvement in energy/bit is 87% as in [1].Further to improve the performance of the CMS-Bias the d-latch can be used as a delay element which consumes less power compared to buffer.
Keywords
Cms Scheme, Interconnects, Process Variation, Signal-ing Scheme and Variation Tolerant.
Cite this article
S. Karthiga Swathini, P. N. Palanisamy, “Efficient On-Chip Interconnects Using CMS Scheme with Variation Tolerant” INTERNATIONAL JOURNAL OF ADVANCED INFORMATION AND COMMUNICATION TECHNOLOGY, pp.512-516, July 05, 2016.
Copyright
© 2016 S. Karthiga Swathini, P. N. Palanisamy. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.