Nilesh S. Wange, Sanjay L. Haridas, Sanjay. B. Tembhurne, G. H. Raisoni Academy of Engineering and Technology, Nagpur, Maharashtra, India.
DOI : 01.0401/ijaict.2014.07.07
International Journal of Advanced Information and Communication Technology
Received On : July 12, 2016
Revised On : August 24, 2016
Accepted On : September 15, 2016
Published On : October 05, 2016
Volume 03, Issue 10
Pages : 569-571
Abstract
In digital communication system, channel coding techniques are mostly use convolutional codes for wireless Applications. For decoding the convolutional codes Viterbi decoder is commonly used, because of its high speed performance. Because of fast developments in the communication systems have generated in increasing demand for high speed and low power Viterbi decoders with long battery life, low power dissipation and low weight. In an Asynchronous Technique various Handshaking signals are used to communicate between blocks. Hence asynchronous designs are inherently data driven and are active only when doing useful work, enabling considerable saving in power and operating at the average speed of all components. The Proposed method is focused on the design of low power consumption of a Viterbi decoder for rate of r=1/2, with a constraint length K=3 by using asynchronous technique. This design will be implemented in Virtex7 field Programmable Gate Array (FPGA) kit.
Keywords
Asynchronous Viterbi Decoder, VHDL.
Cite this article
Nilesh S. Wange, Sanjay L. Haridas, Sanjay. B. Tembhurne, “A Review on Low Power Design for Asynchronous Viterbi Decoder” INTERNATIONAL JOURNAL OF ADVANCED INFORMATION AND COMMUNICATION TECHNOLOGY, pp.569-571, October 05, 2016.
Copyright
© 2016 Nilesh S. Wange, Sanjay L. Haridas, Sanjay. B. Tembhurne. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.