S.A. Ameena Nasreen, T. Kavitha, NPR College of Engineering and Technology, Dindigul, Tamilnadu, India.
DOI : 01.0401/ijaict.2014.01.06
International Journal of Advanced Information and Communication Technology
Received On : April 13, 2015
Revised On : May 15, 2015
Accepted On : June 15, 2015
Published On : July 05, 2015
Volume 02, Issue 07
Pages : 307-312
Abstract
Sub-threshold is a new paradigm in the digital VLSI design today. In Sub-threshold region, transistors are operated in sub-threshold voltage. This paper examine the Carry Look Ahead (CLA) Adder with dual mode logic (DML)principle, in which gates are operated in sub-threshold regime and comparison of results with Conventional basic Carry look ahead adder . The number of gates in CLA is 5 including 2 XOR gates are used to perform sum & 2 NAND, an NOR gates are used to perform carry operations. It allows operation in two modes (Dual mode), very fast in the dynamic mode while energy efficient in the static mode. Critical paths are allowed to operate in dynamic mode. Non-critical paths are allowed to operate in static mode. In this result, speed, energy dissipation. Power consumption of DML based CLA is compared with conventional CLA.
Keywords
Dual Mode Logic, Critical Paths, Dynamic Mode, Non-Critical Paths, Conventional Basic Carry Look Ahead Adder, Static Mode.
Cite this article
S.A. Ameena Nasreen, T. Kavitha, “Design of Carry Look Ahead Adder Using Sub Threshold Dual Mode Logic” INTERNATIONAL JOURNAL OF ADVANCED INFORMATION AND COMMUNICATION TECHNOLOGY, pp.307-312, June 05, 2015.
Copyright
© 2015 S.A. Ameena Nasreen, T. Kavitha. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.