C. Arunima, Vivekanandha College of Engineering for Women, Namakkal, Tamilnadu, India.
Jayaraj. U. Kidavu, Rony Mathew, National Institute of Electronics & Information Technology, Calicut, India.
DOI : 01.0401/ijaict.2014.03.03
International Journal of Advanced Information and Communication Technology
Received On : March 08, 2015
Revised On : April 10, 2015
Accepted On : May 12, 2015
Published On : June 05, 2015
Volume 02, Issue 06
Pages : 294-298
Abstract
Edge detection is one of the most fundamental algorithms in digital image processing. The Canny edge detector is the most common edge detection algorithm because of its ability to detect edges even in images that are highly contaminated by noise. But, this is a time consuming algorithm and hence its implementations are difficult to reach real time response speeds. Especially,in the present days where the demand for high resolution real time image processing is constantly increasing, the need for efficient and fast edge detector implementations is very necessary. In order to obtain maximum efficiency a modified canny algorithm is used in this project which explores the parallel implementation possibilities of the algorithm. A highly parallel and pipelinedarchitecture is used from which real time responses are possible. It is implemented in Field Programmable Gate Array (FPGA).
Keywords
Canny Edge Detection, FPGA, Virtex-6.
Cite this article
C. Arunima, Jayaraj. U. Kidavu, Rony Mathew, “Development of Post Processing IP Core for Ultrasound Imaging” INTERNATIONAL JOURNAL OF ADVANCED INFORMATION AND COMMUNICATION TECHNOLOGY, pp.294-298, June 05, 2015.
Copyright
© 2015 C. Arunima, Jayaraj. U. Kidavu, Rony Mathew. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.