A. Hasna, Vivekanandha College of Engineering for Women, Namakkal, Tamilnadu, India.
Jayaraj. U. Kidavu, Scientist, National Institute of Electronics & Information Technology, Calicut,India.
DOI : 01.0401/ijaict.2014.03.01
International Journal of Advanced Information and Communication Technology
Received On : March 13, 2015
Revised On : April 24, 2015
Accepted On : May 14, 2015
Published On : June 05, 2015
Volume 02, Issue 06
Pages : 279-284
Abstract
The lifting scheme based Discrete Wavelet Transform is apowerful tool for image processing applications. The lack of disk space during transmission and storage of images pushes the demand for high speed implementation of efficient compression technique. This paper proposes a highly pipelined and distributed VLSI architecture of lifting based 2D DWT with lifting coefficients represented in fixed point [2:14] format. Compared to conventional architectures , the proposed highly pipelined architecture optimizes the design which increases significantly the performance speed. The design raises the operating frequency, at the expense of more hardware area. In this paper, initially a software model of the proposed design was developed using MATLAB. Corresponding to this software model, an efficient highly parallel pipelined architecture was designed and developed using verilog HDL language and implemented in VIRTEX 6 (XC6VHX380T) FPGA.The entire system is suitable for several real time applications.
Keywords
Block Syndrome Decoding, TTCM, Iterative Decoding, BSD BICM.
Cite this article
A. Hasna, Mr. Jayaraj, “Design and Implementation of Lifting Based 2D Discrete Wavelet Transform in FPGA” INTERNATIONAL JOURNAL OF ADVANCED INFORMATION AND COMMUNICATION TECHNOLOGY, pp.279-284, June 05, 2015.
Copyright
© 2015 A. Hasna, Mr. Jayaraj. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.