Anjana Sasidharan, Vivekanandha College of Engineering for Women, Namakkal, Tamilnadu, India.
M.K. Arun, Electronics Engineer, TechnoVision, Pune, India.
DOI : 01.0401/ijaict.2014.02.20
International Journal of Advanced Information and Communication Technology
Received On : February 10, 2015
Revised On : March 21, 2015
Accepted On : April 11, 2015
Published On : May 05, 2015
Volume 02, Issue 05
Pages : 274-278
Abstract
IEEE-754 specifies interchange and arithmetic formats and methods for binary and decimal floating-point arithmetic in computer programming world. The implementation of a floating- point system using this standard can be done fully in software, or in hardware, or in any combination of software and hardware. This paper propose VHDL implementation of IEEE -754 Floating point unit .In proposed work the pack, unpack and rounding mode was implemented using the VHDL language and simulation was verified.
Keywords
IEEE754, Floating Point Unit, Pack, Unpack, Rounding.
Cite this article
Anjana Sasidharan, M.K. Arun, “VHDL Implementation of IEEE 754 Floating Point Unit ” INTERNATIONAL JOURNAL OF ADVANCED INFORMATION AND COMMUNICATION TECHNOLOGY, pp.250-253, May 05, 2015.
Copyright
© 2015 Anjana Sasidharan, M.K. Arun. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.