P. Anusha, S. Jayachitra, Vivekanandha College of Engineering for Women, Tamilnadu, India.
DOI : 01.0401/ijaict.2014.02.06
International Journal of Advanced Information and Communication Technology
Received On : November 13, 2014
Revised On : December 11, 2014
Accepted On : January 12, 2015
Published On : February 05, 2015
Volume 02, Issue 02
Pages : 204-208
Abstract
Power reduction is one of the most significant challenges in designing today’s advanced VLSI circuits. Power gating is a technique used in IC design to reduce power consumption by shutting off the current to parts of the circuits which are not in use. In MTCMOS, the large inrush current and ramp up time are arised. We are proposing a new analytical model considering package RLC parasitic for reducing the inrush current and ramp up time. It is possible by analyzing the impact of decoupling capacitances on ramp up time and inrush current. Unlike the previous power sequence method, we are proposing a different inrush current modeling. We can consider our framework as a conservative method to limit the inrush current. So the power up sequence generated by our proposed method can satisfy the inrush current constraint.
Keywords
Inrush Current, Low Power Design, Multi-Threshold Cmos(Mtcmos), Power Gating, Power-Up Sequence, Ramp-Up Time
Cite this article
P. Anusha, S. Jayachitra, “MTCMOS Design for Effective Voltage Drop Control” INTERNATIONAL JOURNAL OF ADVANCED INFORMATION AND COMMUNICATION TECHNOLOGY, pp.204-208, February 05, 2015.
Copyright
© 2015 P. Anusha, S. Jayachitra. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.