P. Anjusha, S. Jayachitra, Vivekanandha College of Engineering for Women, Tamilnadu, India.
DOI : 01.0401/ijaict.2014.02.05
International Journal of Advanced Information and Communication Technology
Received On : November 05, 2014
Revised On : December 29, 2014
Accepted On : January 14, 2015
Published On : February 05, 2015
Volume 02, Issue 02
Pages : 199-203
Abstract
In this paper, we proposed a unified capture scheme for both small delay defect detection (SDD) and online aging prediction. A unified capture scheme can be easily incorporated into the original clock distribution system in the chip. We are introducing a new method to detect the small delay defects without using faster than at speed clock. It will significantly reduce the test power issues. A novel testing strategy can be proposed that is designed to detect small delay defects by creating internal signal races. The races are created by launching transitions along the two paths simultaneously, a reference path and a test path. The arrival time of the transitions on a common or convergence gate will determine the result of the race. The presence of a small delay defect on the test path creates a static hazard on the convergence gate that is directed to the input of a scan –latch. A glitch detector is added to the scan latch to record the presence or absence of the glitch.
Keywords
Small Delay Defect, Online Aging Prediction, Internal Signal Races, Unified Capture, Faster than at Speed Test.
Cite this article
P. Anjusha, S. Jayachitra, “A Novel Method for Small Delay Defect Detection Using Glitch Detector” INTERNATIONAL JOURNAL OF ADVANCED INFORMATION AND COMMUNICATION TECHNOLOGY, pp.199-203, February 05, 2015.
Copyright
© 2015 P. Anjusha, S. Jayachitra. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.