P. P. Neethu Raj, G.Yuvaraj, Vivekanadha College of Engineering for Women, Tiruchengode, Tamilnadu, India.
DOI : 01.0401/ijaict.2014.01.21
International Journal of Advanced Information and Communication Technology
Received On : June 09, 2014
Revised On : July 18, 2014
Accepted On : August 17, 2014
Published On : September 05, 2014
Volume 01, Issue 04
Pages : 107-112
Abstract
A Novel super-pipelined Architecture including viterbi algorithm for implementation of fast fourier transform (FFT) Processors for multiple-input multiple-output Orthogonal frequency division multiplexing (MIMO-OFDM) systems. The super pipelined architecture is capable of achieving high throughput in an area efficient manner. A pipelined architecture is proposed to realize the Viterbi algorithm for moderate speed applications. This architecture can effectively reduce the silicon area necessary for the VLSI implementation of the Viterbi algorithm with the large constraint length. The existing system is a variable length FFT processor forMIMO-OFDM based SDR systems in which butterfly diagram is used in every stage of internal processing. So it will increase the processing time at result it will reduce the speed and take memory to store the each valuein butterfly process. Finally it increases the memory size. It consists of only pipelined architectures. A reduced memory FFT Processor can be implemented by using a Multi path delay commutator (MDC) based architecture. Only one MDC is used in the system and it will be available to every stage, so that the complexity and memory usage can be reduced. The MDC based system is efficient in terms of area but it is not efficient in terms of power. For the speed improvement we are proposing a new system with viterbi algorithm inside the FFT rather than the radix-2 algorithm. It can be applied to various wireless communication applications. The processor was implemented with an UMC90-nm CMOS technology.We are implementing the FFT processor with radix -2 algorithms that includes only one MDC for reducing the memory. A super- pipelined architecture based FFT processor for moderate speed application with reduced memory is proposed. An ACS (adds, compare and select) unit for the viterbi decoder with the constraint length 7 is designed to demonstrate the feasibility of this architecture in a 0.6 μm 3.3V triple-metal CMOS process.
Keywords
Fast fourier transform(FFT); Multiple-input multiple-output(MIMO); Orthogonal frequency division multiplexing(OFDM); Multi path delay commutator(MDC).
Cite this article
P. P. Neethu Raj, G.Yuvaraj, “A High Speed FFT / IFFT Processor for MIMO OFDM Systems” INTERNATIONAL JOURNAL OF ADVANCED INFORMATION AND COMMUNICATION TECHNOLOGY, pp.107-112, September 05, 2014.
Copyright
© 2014 P. P. Neethu Raj, G.Yuvaraj. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.