Deepa Singh, Banasthali Vidyapith, Rajasthan, India.
DOI : 01.0401/ijaict.2014.01.15
International Journal of Advanced Information and Communication Technology
Received On : May 07, 2014
Revised On : June 10, 2014
Accepted On : July 15, 2014
Published On : August 05, 2014
Volume 01, Issue 04
Pages : 076-078
Abstract
In recent years, sub-threshold logic and body biastechnique provides ultra low power and high speed operation. Therefore, sub-threshold circuit design is very promising for future ultra low-energy sensor applications, pace maker as well as high-performance parallel processing. Sub-threshold logic is the new technique to overcome the problem of performance and delay. New methodology and topology is used for the designing of sub-threshold circuit. The main focus of this paper is to reduce the overall leakage by sub-threshold logic with body bias technique. We will design and simulate the 1 Bit full adder and see the result.Circuit simulations were conducted using 180nm CMOS technology to validate proposed concept. The results were compared with standard body bias technique in terms of leakage reduction.
Keywords
Sub-threshold logic; Body bias; low power;1 bit full adder
Cite this article
Deepa Singh, “Leakage Reduction in One Bit Full Adder Using Sub Threshold Logic with Body Bias Effect” INTERNATIONAL JOURNAL OF ADVANCED INFORMATION AND COMMUNICATION TECHNOLOGY, pp.076-078, August 05, 2014.
Copyright
© 2014 Deepa Singh. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.