M. Aswathi Mohan, M. Ramkumar Raja, Coimbatore Institute of Engineering and Technology, Coimbatore, Tamilnadu, India.
DOI : 01.0401/ijaict.2014.01.06
International Journal of Advanced Information and Communication Technology
Received On : April 18, 2014
Revised On : May 21, 2014
Accepted On : June 15, 2014
Published On : July 05, 2014
Volume 02, Issue 03
Pages : 059-062
Abstract
A high speed security algorithm is always important for wired/wireless environment. The Advanced Encryption Standard (AES) is a specification for the encryption of electronic data. This is called Rijndael. The algorithm described by AES is a symmetric-key algorithm that is the same key is used for both encrypting and decrypting the data. AES has the advantage of being implemented in both hardware and software. The AES hardware was implemented in three modules contains of the encryption, the decryption and the key scheduling module. The implementation of pipelined cryptography hardware is used to improve performance in order to achieve higher throughput and greater parallelism. Here the delay is been reduced ten times than that of normal AES architecture. Registers in pipelined structure can be replaced by low power register for power optimization. Xilinx design suite 14.5 is used for the implementation.
Keywords
Cryptography, AES, DES, Efficient encryption decryption implementation, Pipeline.
Cite this article
M. Aswathi Mohan, M. Ramkumar Raja, “Delay Optimization in Advanced Encryption Standard Architecture” INTERNATIONAL JOURNAL OF ADVANCED INFORMATION AND COMMUNICATION TECHNOLOGY, pp.059-062, July 05, 2014.
Copyright
© 2014 M. Aswathi Mohan, M. Ramkumar Raja. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.