Shanmugaraja T and Supriya M, Assistant Professor/ECE, KPR Institute of Engineering and Technology, Coimbatore, India
Kavin kumar K, Assistant Professor (Senior Grade)/ECE, Kongu Engineering College, India
Godwin Cryil N, Assistant Professor/ECE, Sethu Institute of Technology, Technical lead, Oath Electronics, Bangalore, India
Pradeep M, Assistant Consultant TATA Consultancy Services, India
Online First : 30 December 2020
Publisher Name : IJAICT India Publications, India.
Print ISBN : 978-81-950008-0-7
Online ISBN : 978-81-950008-1-4
Page :401-406
Abstract
In this article presents an HDL template on the ASIC platform. For quicker and safer image data transmission stable encoding of pictures via image compression and AES through encryption, the DWT was facilitated. The DWT calculation algorithm based on a lifting scheme and a multi-level sub-bands on the ASIC platform are created. 2D-DWT was built using it. The related sub-bands were chosen to minimize the compression time of the AES encryption, based on compression ratio and data recovery. To ensure high efficiency and latency, the DWT architecture was developed HDL model and AES algorithm for the area, timing and power performance of the ASIC platform have been developed and validated for the DWT architecture. Using 56 nm CMOS technology, the ASIC implementation was carried out.
Keywords
Encoding, data recovery, encryption, CMOS.
Cite this article
Shanmugaraja T, Supriya M, Kavin kumar K, Godwin Cryil N and Pradeep M, “Efficient Low Power Region Enhanced Architectures For DWT And AES For Protected Coding Image”, Innovations in Information and Communication Technology, pp. 401-406, December 2020.
Copyright
© 2020 Shanmugaraja T, Supriya M, Kavin kumar K, Godwin Cryil N and Pradeep M,. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.
