P. Anitha, Department of ECE Sri Krishna College of Engineering and Technology, India.
Dhivya devi R and Siddharthraju K, Department of ECE KPR Institute of Engineering and Technology, India .
Boobathi S, Associate General Manager BigCat Wireless Pvt Ltd., India.
Online First : 30 December 2020
Publisher Name : IJAICT India Publications, India.
Print ISBN : 978-81-950008-0-7
Online ISBN : 978-81-950008-1-4
Page :087-090
Abstract
VLSI is the relating to more than one branch of science of utilizing the advanced semiconductor technology to develop various functional units of computational System. The most complex function carried out by ALU is multiplication. Digital multiplication is most extensively used operation particularly in signal processing, System designer has to sacrifice silicon die area in order to make the multiplication as soon as possible. In this paper, various multiplier architectures are simulated and compared with high speed and low power 8x8 Vedic multiplier (Urdhva Triyagbhayam) which uses modified carry select adder for partial product reduction. The design is implementation and simulation has been done by Microwind tool with 90 nm technology. The simulation result shows 58% of power reduction, 65% of delay reduction and 44% of area reduction has been attained.
Keywords
Wallace, Dadda, Vedic multiplier, Partial Product Array Reduction, Power delay product (PDP).
Cite this article
P. Anitha, Dhivya devi, Siddharthraju K and Boobathi S, “Investigation on Low Power Digital Tree Multipliers”, Innovations in Information and Communication Technology, pp. 087-090, December 2020.
Copyright
© 2020 P. Anitha, Dhivya devi, Siddharthraju K and Boobathi S. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.
