Innovations in Information and Communication Technology


Advances in Computing, Communication, Automation and Biomedical Technology


An Improved VLSI Design of 16 Bit Data Comparator using Bubble Sorting Algorithm

Ramesh S M, Department of ECE KPR Institute of Engineering & Technology, India.

Gomathy B, Department of CSE KPR Institute of Engineering & Technology, India.

Mahes Kumar P, Dept. of EEE Lords Institute of Engg & Tech Hyderabad, India.

Balaji G, Electric Power Streering System Robert Bosch EBS Ltd, India.

Online First : 30 December 2020

Publisher Name : IJAICT India Publications, India.

Print ISBN : 978-81-950008-0-7

Online ISBN : 978-81-950008-1-4

Page :063-068

Abstract


Comparator is an important arithmetic component on a digital circuit. Here the major goal of this project is to design a data comparator, which gives the sparing solution for sorting the data on the basis of power, area, and speed. Sorting is one of the problems in computer engineering/science. In computing system or/and communication systems, many important processes require the sorting of data. Here, the proposed work comprises the design of 16 Bit Comparator with Bubble sorting algorithm. This proposed comparator design is targeted for 6slx4tqg144-3 using Xilin ISE compiler tool by verilog model. The bubble sort algorthm also referred to the sinking sort algorithm. By this process, based on the adjancy pair of data, this will swap/interchange their positions/location. Here the proposed system is also design the 16 Bit Magnitude comparator for reducing delay factor of the system and the comparator design uses behavioural style for reducing the power factor. The overall system design optimizes the area by reducing the number of unwanted LUT block in the design. Since this proposed system gives the better result as compared to the conventional method by getting the result of power, area, and delay. The overall design is compiled through Xilinx 14.5 software and it is simulated by Modelsim tool.

Keywords


Data Comparator, Bubble sorting Algorithm, Power, Area and Delay reduction, Verilog

Cite this article


Ramesh S M, Gomathy B, Mahes Kumar P, Balaji G, “An Improved VLSI Design of 16 Bit Data Comparator using Bubble Sorting Algorithm”, Innovations in Information and Communication Technology, pp. 063-068, December 2020.

Copyright


© 2020 Ramesh S M, Gomathy B, Mahes Kumar P, Balaji G. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.